The present invention works in combination with an integrated set of hardware and software tools that support rapid design, programming, debugging, implementation, and testing of local operation network nodes and applications. These hardware and software tools speed development by enabling developers to use object-oriented concepts, such as network variables and input/output objects, rather than low-level constructs.
The development environment operates with an IBM PC/AT or compatible computer and can grow from a single emulated application node to a completely distributed system of up to 24 emulated nodes and hundreds of remote nodes.
Network design, hardware design, and software design are all independent to allow hardware, software, and network development to proceed in parallel. Maintenance time is saved because nodes that have already been programmed need not be reprogrammed each time the network is reconfigured.
During development, local operation network-based applications typically grow from a pair of communicating nodes to large networks of many nodes. Because the hardware development environment must grow with the application, the hardware and software tools support testing of one or two nodes but are capable of expanding too many nodes.
The tools provide an expandable hardware environment with a development station and processor boards. In one embodiment, each development station includes two built-in nodes for managing and monitoring the developer's network and can accommodate up to six processor boards in a cardcage. An interface adaptor installed in the host PC provides high speed communications between the PC and up to four development stations.
Processor boards may be added to each development station to create local operation network application nodes. Each processor board supports one application node. The processor boards accept optional expansion boards that may be used for developing prototype I/O interfaces and transceivers. Transceiver evaluation boards allow for twisted pair, RF, and powerline communications. The developer may also develop custom I/O or transceiver expansion boards.
To simplify network development, the hardware and software tools are independent of the communications medium. Initial development may start with communications occurring over a backplane network built into the development station. Transceiver expansion boards can be added or changed at any time to change the network medium without affecting the software design. Communications across multiple channels and multiple media are supported with router boards.
Nodes are initially developed on a Neuron Emulator, which is a local operation network node that supports source-level debugging and hardware prototypinq. The Neuron Emulator is a processor board which incorporates a 3150 Neuron chip with 64 Kbytes of RAM available from Echelon Corporation of Palo Alto, Calif. which is the owner of the term Neuron as a trademark for the processors and related products sold by Echelon Corporation. Software may be executed independent of target hardware to enable software development to occur even before hardware is available. Each emulator board can have one or two expansion boards for testing with prototype I/O and/or transceiver hardware.
The emulator provides hardware support for fast application download, source-level breakpoints, single-stepping, reset/start/halt, and memory read/write protection. In one embodiment, the emulator also provides a software controlled clock rate that may be set to 10 MHz, 5 MHz, 2.5 MHz, 1.25 MHz, or 625 KHz. A suitable emulator board for use with the present invention is available from Echelon Corporation.
The hardware tools used in conjunction with the present invention typically include a complete single board computer (SBC) that may be used within the development station or used remotely with a transceiver and user-supplied power to create a physically distributed network environment. Once the application software is debugged on the emulator, it may be moved away from the development station using the SBC. In one embodiment, the SBC incorporates a 3150 Neuron chip with 64 Kbytes of non-volatile RAM. The SBC accepts the same I/O and media interface expansion boards as the emulator so that prototype 1/O and transceiver hardware may be tested in a remote node. A suitable SBC is available from Echelon Corporation.
Networks with multiple channels and media may be constructed during development with the router board. In one embodiment, the router board is a processor board incorporating two 3150 Neuron chips and connections for two transceivers designed to provide routing between two network channels. The router may be configured as a learning router, a configurable router, or a bridge. When configured as a learning router, the router monitors network traffic to learn the network topology. The router uses the network topology information to selectively route packets between channels. When operated as a configurable router, the router can use routing tables specified with the network management commands available in the software tools. When configured as a bridge, the router forwards all packets between the two connected channels. A suitable router board for use in conjunction with the present invention is available from Echelon Corporation. The router may be housed inside the development station or operated remotely with a user-supplied external power supply.
Transceiver evaluation boards are optional expansion boards that may be installed on any processor board to provide the physical interface to a local operation network network channel. Suitable transceiver evaluation boards are available from Echelon Corporation for twisted pair, powerline, and RF media.
The 3150 Neuron chip in an emulator board can interface directly with a backplane network to communicate within a limited distance. A twisted-pair transceiver evaluation board can be used to extend prototype networks to the maximum topological and performance boundaries of a local operation network on the twisted-pair media. The units are required in applications that require long distances and a large number of nodes on the network. Twisted pair transceiver evaluation boards are also required to support collision detection on twisted-pair networks. A suitable twisted-pair transceiver evaluation board supporting two data rates: 1.25 Mbps and 78 Kbps is available from Echelon Corporation.
A suitable powerline transceiver evaluation board available from Echelon Corporation provides the physical interface for 90-277 VAC powerlines. The powerline transceiver evaluation unit provides a 9766 bps data rate modulated on high frequency carrier signals. The powerline evaluation unit is typically housed in a stand-alone enclosure that connects to an expansion board mounted on any development station processor board. The stand-alone enclosure includes a power supply for the evaluation unit and provides a +5V, 1.4A output to support a remote SBC.
A suitable radio frequency transceiver evaluation board available from Echelon Corporation provides the physical interface to a radio frequency network. The radio frequency transceiver Evaluation Board provides a 4883 bps data rate using a 49 MHz carrier, and supports reliable communications within buildings at distances up to 30 feet.
Suitable software or application programming tools to provide all the tools required to edit, compile, and debug Neuron C applications, which is the programming language used by the 3150 Neuron chips, are available from Echelon Corporation. The tools are integrated, thereby reducing training time and increasing productivity.
Application programming is supported using an Integrated Development Environment (IDE), also available from Echelon Corporation. The IDE automates the development cycle and provides a common framework for all the software tools. The IDE includes an object database that stores the definition of all objects defined by the user. The object database ensures consistency and simplifies use of the development system since all tools share a common definition of the application.